1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to an improved passivation layer to be formed on a metal wiring layer of a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
The semiconductor surface and the metal surface layers are usually protected with a covering dielectric. This dielectric is called the passivation layer, and is often the outermost layer of the semiconductor device to protect the device from stress applied during package molding and harmful environment such as contamination and moisture. The passivation layers are sometimes interposed between multiple metal wiring layers to function as interlayer dielectrics.
There are known the passivation layers such as a silicon dioxide layer (SiO.sub.2) and a phospo-silicate glass layer (PSG) formed by CVD (chemical vapor deposition), and a silicon nitride layer (P-SiN) and a silicon dioxide layer (P-SiO) formed by PCVD (plasma-assisted chemical vapor deposition).
With minimization of the semiconductor device elements, the passivation layers are required to have various characteristics. Specifically, these characteristics are resistant to thermal and mechanical stress to be applied during the subsequent manufacturing stages after formation of the passivation layers, insulation from the atmospheric conditions, especially moisture, and insulation from alkali metals like Na.sup.+. Along with minimization of the semiconductor devices and multiplication of the wiring metal layers, electro-migration (EM) and stress migration (SM) are noted as troubles related to the semiconductor devices. These troubles are found to be resultant from intrinsic stress relative to the passivation layers.
The CVD SiO.sub.2 and PSG layers do not satisfy the mechanical strength required for the passiviation layer. Since these layers are formed at relatively high temperatures, they have little hydrogen content and cannot function sufficiently as a protective layer because of insufficient moisture resistivity. With the CVD passivation layer, the intrinsic stress of the layer functions as tensile stress, which causes cracks when the layer is being formed.
With the PCVD P-SiN and P-SiO layers, the intrinsic stress functions as compressive stress, which is useful to suppress cracks during the layer formation. Since these layers are formed at relatively low temperatures, they have larger hydrogen content than the CVD layers, and are superior to the CVD layers in the moisture resistivity.
As for the mechanical strength, the P-SiO layer is inferior to the P-SiN layer but superior to the CVD layers, and is inferior to the P-SiN layer to passivate the minute patterns and to block alkali ions.
Therefore, the P-SiN layer seems superior to the other layers as the passivation layer. However, the P-SiN layer has the intrinsic compressive stress higher than that of the P-SiO layer. The thicker the P-SiN layer, the more the compressive stress. Generally speaking, the passivation layer should be at least 1 .mu.m thick to prevent pinholes. When it is about 1 .mu.m thick, the P-SiN layer tends to increase its intrinsic stress, which adversely affects underlying wiring layers, leading to deterioration of resistivity to the electro-stress migration of the minimized semiconductor devices.
When any of these layers is used to form a single passivation layer with a required thickness, the passivation layer does not have all the required properties. To overcome this difficulty, dual layer passivation is proposed in U.S. Pat. No. 4,446,194, for example, which discloses that a first passivation layer is a PCVD P-SiO layer, and a second passivation layer is a CVD SiO.sub.2 layer. The first P-SiO layer has the intrinsic stress, which serves as the compressive stress to lessen the residual tensile strength of the metal layer and to reduce void formation due to stress- or electro-migration. This dual layer passivation however does not seem sufficient to improve resistivity to electro-stress migration of extensively minimized semiconductor devices. The double layer structure of the oxide layers does not provide the mechanical strength identical to the mechanical strength of the P-SiN layer, and is rather inferior in the alkali ion blocking capability. The first, SiO.sub.2 layer does not have sufficient moisture resistivity causing moisture to enter into a border between the first and second passivation layers. The first and second passivation layers are formed by the different deposition methods, which means reduced throughput of the semiconductor devices.
As described above, the existing passivation layers are rather insufficient for protection of minute metal wiring layers. At present, various efforts have been made to improve the metal wiring layers to overcome the problems related to the electro-stress migration.